This invention relates to a velocity error compensator and, more particularly, to a digital velocity error compensator that is used in a time base corrector, such as a video signal time base corrector.
Time base errors, which are frequency and/or phase errors, often are introduced into information signals that are reproduced from a record medium. For example, when video signals are recorded on a magnetic tape, such as by a video tape recorder (VTR), time base errors may be introduced into those video signals when they are played back. Such time base errors are due to, for example, expansion or contraction of the magnetic tape after the video signals have been recorded thereon; a change in the speed at which the magnetic tape is driven during the playback mode than during the recording mode; changes in the speed at which the playback heads scan the magnetic tape during recording and playback modes in a so-called helical-scan VTR; and the like. When the reproduced video signals are displayed on a television monitor, or receiver, the time base errors that may be present therein appear as undesired effects such as jitter, brightness distortion, erroneous color display, and the like.
Time base correctors are known whereby the aforementioned time base errors are substantially eliminated from the reproduced video signals. One example of a time base corrector is found in U.S. Pat. No. 3,860,952. Typically, the reproduced video signals are converted from their usual analog form into digital form, and the digitized video signals are stored temporarily in a digital memory. Successive samples of the video signal are written into the memory at a write-in clock rate that is synchronized with the detected time base errors. Once a line of video signal samples is stored, the stored samples are read out, one at a time, at a standard, fixed read-out clock rate. Since the video signal samples are written in in synchronism with the time base errors and are read out at a fixed rate, the time base errors are substantially removed. The read out video signal samples then are reconverted back into analog form and may be displayed, transmitted, or otherwise processed, free of undesired time base errors.
The typical time base corrector of the type described above does not take velocity errors into account. The velocity error of a video signal is the time base error which may exist over all, or a substantial portion, of a horizontal line interval. In typical time base correctors, the horizontal synchronizing signal and usual burst signal are detected at the beginning of a line interval; and the write clock generator which is used to generate write-in clock pulses that are synchronized with the time base error is frequency and phase-locked to such synchronizing and burst signals. The phase-locking of the write-in clock pulses occurs at the beginning of each horizontal line interval because the burst signal is present in the video signal only at that time. There is no adjustment or correction in the phase of the write-in clock pulses throughout the remainder of the horizontal line interval. However, the timing, or phase, of the video signal may vary during that line interval. For example, the phase of the chrominance subcarrier upon which the chrominance component is modulated may vary. It is this unaccounted for time or phase variation of the video signal during the horizontal line interval that is referred to as the "velocity error". Of course, at the end of the line interval or, more accurately, at the beginning of the next-following line interval, the overall extent of the velocity error can be ascertained merely by sensing the amount of phase adjustment that is needed to bring the write-in clock pulses into proper phase synchronism with the burst signal. That is, in the usual automatic phase control (APC) circuit, the write clock phase control signal provides a good indication of the extent of the velocity error which was present in the immediately preceding line interval.
It has been proposed to provide time base correctors of the aforementioned type with velocity error correcting circuitry. For example, in U.S. Pat. No. 4,120,000, the velocity error of each line of reproduced video signals is stored as a velocity error correcting voltage. This voltage is produced by comparing the phase of the time base corrector write-in clock pulses to the phase of the burst signal in each line interval, and the velocity error correcting voltage is produced as a function of any phase differential therebetween. When a line of video signals is read out from the time base corrector memory, the velocity error correcting voltage associated with that line is integrated over a period of time equal to a horizontal line interval, thus producing a linearly changing velocity error signal, which signal is used to phase modulate the read-out clock pulses. Hence, the video signals are read out of the time base corrector memory at a phase-modulated rate which is assumed to be a close approximation of the actual velocity error that was present in the line of video signals that had been written into the memory.
In the aforementioned patent, the velocity error in each line of video signals written into the time base corrector memory is assumed to vary linearly throughout the entire line interval. Another velocity error corrector which proceeds on this assumption is described in U.S. Pat. No. 4,065,787.
Other velocity error correcting circuits have been proposed wherein the velocity error is assumed to be not necessarily linear, or uniform, throughout the entire line interval. For example, in U.S. Pat. No. 4,165,524, the read-out clock pulses are phase modulated at different rates during a line interval, these different rates being a function of the velocity error that is present in preceding and succeeding line intervals. Also, in copending U.S. Pat. No. 4,393,413, filed Mar. 16, 1981, the velocity errors which are present in three successive line intervals are combined and integrated to produce a nonlinear velocity error correcting signal which then is used to phase modulate the time base corrector memory read-out clock pulses.
In all of the aforementioned velocity error correcting systems, velocity errors are corrected by varying the phase, or times of occurrence of the read-out clock pulses. The video signal samples, which are represented as multi-bit digital signals are read out of the time base corrector memory at phase-adjusted times. Although the effective magnitudes, or values, of the samples are not altered, the phase modulation of the read-out clock pulses results in compensating for the velocity errors when the read-out samples are reconverted back into analog form. Thus, velocity error correction is not made in the digitized video signals but, rather, is effected when the video signals are reconverted into analog form.
It is desirable, in many instances, to obtain a velocity error-corrected digital video signal. In accordance with the velocity error correction techniques described above, this has been achieved heretofore only by reconverting the velocity error-corrected analog video signal back into digital form. This, of course, is accompanied by the usual quantization noise and inherent errors in any digital-analog-digital conversion. Thus, it is desirable to provide a digital velocity error compensator so that digital-to-analog conversion and phase modulation of read-out clock pulses can be avoided.